Technical Program

Presentation Guidelines

    Monday July 15th (Tata Innovation Center, Room 023 & 131)
    8:30-9:00 Registration
    9:00-9:15 Welcome Remarks (Slides)
    9:15-10:00 Keynote I (Chair: Zhiru Zhang)
    DNA Data Storage and Near-Molecule Processing for the Yottabyte Era

    Luis Ceze, University of Washington
    10:10-10:50 Paper Session – Applications: Machine Learning I (Chair: Roger Moussalli, Two Sigma)
    26 F-E3D: FPGA-based Acceleration of An Efficient 3D Convolutional Neural Network for Human Action Recognition (Best Paper Nominee) (Slides)
    Hongxiang Fan1, Cheng Luo3, Chenglong Zeng2, Martin Ferianc1, Zhiqiang Que1, Shuanglong Liu1, Xinyu Niu1, Wayne Luk1
    Imperial College London1, Fudan University2, Corerain Technologies3
    80 LP-BNN: Ultra-low-Latency BNN Inference with Layer Parallelism (Slides)
    Tong Geng1,2, Tianqi Wang1, Chunshu Wu1, Chen Yang1, Shuaiwen Leon Song2, Ang Li2, Martin Herbordt1
    Boston University1, Pacific Northwest National Laboratory2
    10:50-11:10 Coffee Break
    11:10-11:50 Paper Session – Applications: Machine Learning II (Chair: Roger Moussalli, Two Sigma)
    37 Efficient Weight Reuse for Large LSTMs (Slides)
    Zhiqiang Que1, Thomas Nugent1, Shuanglong Liu1, Li Tian3, Xinyu Niu2, Yongxin Zhu3, Wayne Luk1
    Imperial College London1, Chinese Academy of Sciences2, Corerain Technologies Ltd.3
    60 Photonic Processor for Fully Discretized Neural Networks (Slides)
    Jeff Anderson, Shuai Sun, Yousra Alkabani, Volker Sorger, Tarek El-Ghazawi
    George Washington University
    11:50-12:10 Lightning Session for Posters (Slides) (Chair: Cunxi Yu, University of Utah)
    Transparent Heterogeneous Cloud Acceleration (16)
    Jessica Vandebon1, Jose ́ G. F. Coutinho1, Wayne Luk1, Thomas Chau2
    Imperial College London1, Intel2
    CRbS:A Code Reordering based Speeding-up Method of Irregular Loops On CMP (24)
    Yuancheng Li, Jiaqi Shi
    Xi'an University of Science and Technology
    Impact of Structural Faults on Neural Network Performance (51)
    Krishna Teja Chitty-Venkata and Arun Somani
    Iowa State University
    Energy-Efficient Near-Sensor Convolution using Pulsed Unary Processing (99)
    M. Hassan Najafi1, S. Rasoul Faraji2, Kia Bazargan2, and David Lilja2
    University of Louisiana Lafayette1, University of Minnesota Minneapolis2
    An Efficient Application Specific Instruction Set Processor (ASIP) for Tensor Computation (101)
    Wei-pei Huang, Ray C.C. Cheung, Hong Yan
    City University of Hong Kong
    MITRACA: Manycore Interlinked Torus Reconfigurable Accelerator Architecture (102)
    Riadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku
    University of Tsukuba
    DeltaNet: Differential Binary Neural Network (103)
    Yuka Oba1, Kota Ando1, Tetsuya Asai1, Masato Motomura2, Shinya Takamaeda-Yamazaki1,3
    Hokkaido University1, Tokyo Institute of Technology2, JST PRESTO3
    Using Residue Number Systems to Accelerate Deterministic Bit-stream Multiplication (106)
    Kamyar Givaki1, Reza Hojabr1, M. Hassan Najafi2, Ahmad Khonsari1,3, M. H. Gholamrezayi4, Saeid Gorgin5, Dara Rahmati4
    University of Tehran1, University of Louisiana Lafayette2, Institute for Research in Fundamental Sciences Iran3 Shahid Beheshti University4, Iranian Research Organization for Science and Technology5
    Precision Adaptation for Fast and Accurate Polynomial Evaluation Generation (108)
    Nicolas Brunie1, Christoph Lauter2, Guillaume Revy3,4
    Kalray S.A.1, University of Alaska Anchorage2, University of Perpignan Via Domitia3, University of Montpellier4
    12:10-13:30 Lunch & Poster Session I
    Short papers (11, 49, 74, 96) and Posters (16, 24, 51, 99, 101, 102, 103, 106, 108)
    13:30-14:15 Keynote II (Chair: Wayne Luk)
    From AI1.0, AI2.0, to XAI3.0

    Sun-Yuan Kung, Princeton University
    14:25-15:30 Paper Session - Architecture and Synthesis (Chair: Sang-Woo Jun, UC Irvine)
    9 Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays (Slides)
    Bradley McDanel1, HT Kung1, Sai Qian Zhang1, Xin Dong1, Chih Chiang Chen2
    Harvard University1, MediaTek2
    43 Sparstition: A Partitioning Scheme for Large-Scale Sparse Matrix Vector Multiplication on FPGA (Slides)
    Bjorn Sigurbergsson1, Tom Hogervorst1, Tong Dong Qiu2, Razvan Nane1,2
    TU Delft1, Big Data Accelerate2
    31 End-to-end Dynamic Stream Processing on Maxeler HLS Platforms (Slides)
    Charalampos Kritikakis, Dirk Koch
    University of Manchester
    11 (Short) Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration (Slides)
    Pareesa Ameneh Golnari1, Sharad Malik2
    Google1, Princeton University2
    74 (Short) HelmGemm: Managing GPUs and FPGAs for transprecision GEMM workloads in containerized environments (Slides)
    Dionysios Diamantopoulos
    IBM Research Zurich
    15:30-15:50 Coffee Break
    15:50-17:00 Paper Session – Applications: Machine Learning, Robotics, and Simulation I (Chair: Bo Yuan, Rutgers)
    30 Error Analysis of the Square Root Operation for the Purpose of Precision Tuning: a Case Study on K-means (Slides)
    Oumaima Matoussi1, Yves Durand1, Olivier Sentieys2, Anca Molnos1
    CEA, LETI, University Grenoble Alpes1, Univ. Rennes2
    50 FPGA Architectures for Real-time Dense SLAM (Best Paper Award) (Slides)
    Quentin Gautier, Alric Althoff, Ryan Kastner
    UC San Diego
    28 Customizable Control Policy Learning for Robotics (Slides)
    Ce Guo1, Wayne Luk1, Stanley Loh Qing Shui1, Alexander Warren2, Joshua Levine2
    Imperial College London1, Intel2
    49 (Short) Resilient Neural Network Training for Accelerators with Computing Errors (Slides)
    Dawen Xu1,3, Kouzi Xing2, Cheng Liu1, Ying Wang1, Yulin Dai2, Long Cheng3, Huawei Li1, Lei Zhang1
    Chinese Academy of Sciences1, Hefei University of Technology2, University College Dublin3
    76 (Short) VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing (Slides)
    Dilshan Kumarathunga, Omega Gamage, Asitha Samarasinghe, Nipuna Saranga, Ranga Rodrigo, Ajith Pasqual
    University of Moratuwa
    17:10-17:20 Announcement by ASAP'20 Chair
    17:30-21:00 Reception -- Peking Duck House, 236 E 53rd St, Midtown, New York City [direction] [more info]
    Tuesday July 16th (Bloomberg Center, Room 161 & 165)
    09:00-09:45 Keynote III (Chair: Yun (Eric) Liang, Peking University)
    Heterogeneous Systems Research - in the Mood for AI in the age of Cloud and IoT

    Jinjun Xiong, IBM T.J. Watson Research Center
    10:00–10:40 Invited Session: Hardware Acceleration (Chair: Yun (Eric) Liang, Peking University)
    Agile FPGA Design (Slides)
    Justin Thiel, Two Sigma
    PAI-FCNN: FPGA based inference system for complex CNN models (Slides)
    Lixue Xia, Lansong Diao, Zhao Jiang, Hao Liang, Kai Chen, Li Ding, Shunli Dou, Zibin Su, Meng Sun, Jiansong Zhang, Wei Lin
    Alibaba Group
    10:40-11:00 Coffee Break
    11:00-11:45 Paper Session - Applications: Image Processing, Networking, and Floating Point Arithmetic I (Chair: Guojie Luo, Peking University)
    66 Event-Based Re-configurable Hierarchical Processors for Smart Image Sensors (Slides)
    Pankaj Bhowmik, Md Jubaer Hossain Pantho, Christophe Bobda
    University of Florida
    69 OpenVX Graph Optimization for Visual Processor Units (Slides)
    Madushan Abeysinghe1, Jesse Villarreal2, Lucas Weaver2, Jason D. Bakos1
    University of South Carolina1, Texas Instruments Corporation2
    44 (Short) Application Specific Architecture for Hardware Accelerating HOG-SVM to achieve High Throughput on HD Frames (Slides)
    Piyumal Ranawaka1, Mongkol Ekpanyapong2, Adriano Tavares3, Jorge Cabral2, Krit Athikulwongse3, Vitor Silva4
    University of Moratuwa1, Asian Institute of Technology2, National Science and Technology Development Agency3, University of Minho4
    11:45-12:00 Lightning Session for Posters (Slides) (Chair: Cunxi Yu, University of Utah)
    A Quantitative Approach for Refactoring NFV-based Mobile Core Networks (21)
    Wei-Kuo Chiang, He-Xin Chen
    National Chung Cheng University
    Fooling AI with AI: An Accelerator for Adversarial Attacks on Deep Learning Visual Classification (33)
    Haoqiang Guo1, Lu Peng1, Jian Zhang1, Fang Qi1, Lide Duan2
    Louisiana State University1, Alibaba Group2
    A Virtual Image Accelerator for Graph Cuts Inference on FPGA (53)
    Tianqi Gao1, Rob A. Rutenbar2
    University of Illinois at Urbana Champaign1, University of Pittsburgh2
    Implications for Hardware Acceleration of Malware Detection (67)
    Jordan Pattee, Byeong Kil Lee
    University of Colorado, Colorado Springs
    GPUs Pipeline Latency Analysis (93)
    Yehia Arafa1, Abdel-Hameed A. Badawy1,2, Gopinath Chennupati2, Nandakishore Santhi2, Stephan Eidenbenz2
    New Mexico State University1, Los Alamos National Laboratory2
    Context-Aware Number Generator for Deterministic Bit-stream Computing (100)
    Sina Asadi and M. Hassan Najafi
    University of Louisiana Lafayette
    Smart Rabbit: A Wearable Device As Intelligent Pacer for Marathon Runners (110)
    Wenpei Zheng, Sheng-Yang Chiu, Jui-Chien Hsieh, Chaochang Chiu
    Yuan Ze University
    12:00-13:20 Lunch & Poster Session II
    Short papers (17, 44, 57, 68, 73, 95) and Posters (21, 33, 53, 67, 93, 100, 110)
    13:20-14:20 Invited Session: In Memory Computing (Chair: Zhiru Zhang, Cornell University)
    Real Processing-in-Memory with Memristive Memory Processing Unit (Slides)
    Shahar Kvatinsky, Technion – Israel Institute of Technology
    PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations (Slides)
    Oscar Castañeda, Maria Bobbett, Alexandra Gallyas-Sanhueza, and Christoph Studer
    Cornell University
    Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design (Slides)
    Feng Wang, Guojie Luo, Guangyu Sun, Jiaxi Zhang, Peng Huang, Jinfeng Kang
    Peking University
    14:30-15:20 Paper Session – Applications: Machine Learning, Robotics, and Simulation II (Chair: Jieming Yin, AMD)
    71 An Overlay Architecture for High-Throughput Pattern Matching (Slides)
    Rasha Karakchi, Charles A. Daniels, Jason D. Bakos
    University of South Carolina
    59 Towards Real Time Radiotherapy Simulation (Slides)
    Nils Voss1,3, Peter Ziegenhein3, Lukas Vermond2,4, Joost Hoozemans2, Oskar Mencer2, Uwe Oelfke3, Wayne Luk1, Georgi Gaydadjiev1,2,4
    Imperial College London1, Maxeler Technologies2, The Institute of Cancer Research and The Royal Marsden NHS Foundation Trust3, Delft University of Technology4
    68 (Short) Accelerating AP3M-Based Computational Astrophysics Simulations with Reconfigurable Clusters (Slides)
    Tianqi Wang1, Tong Geng2, Xi Jin1, Martin Herbordt2
    University of Science and Technology of China1, Boston University2
    17 (Short) A Programmable Architecture for Robot Motion Planning Acceleration (Slides)
    Sean Murray1, Will Floyd-Jones1, George Konidaris2, Dan Sorin1
    Duke University1, Brown University2
    15:20-15:40 Coffee Break
    15:40-16:40 Paper Session - Emerging Technologies (Chair: Jason Bakos , University of South Carolina)
    109 Leveraging Energy Cycle Regularity to Predict Adaptive Mode for Non-volatile Processors (Slides)
    Zejun Shi1, Dongqin Zhou2, Keni Qiu2, Jiwu Shu1
    Tsinghua University1, Capital Normal University2
    58 An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators (Slides)
    Saunak Saha, Henry Duwe, Joseph Zambreno
    Iowa State University
    10 Improving Emulation of Quantum Algorithms using Space-Efficient Hardware Architectures (Slides)
    Naveed Mahmud, Esam El-Araby
    University of Kansas
    95 (Short) Combining Clock and Voltage Noise Countermeasures against Power Side-Channel Analysis (Slides)
    Jacqueline Lagasse, Christopher Bartoli, Wayne Burleson
    University of Massachusetts Amherst
    16:40-17:30 Paper Session - Applications: Image Processing, Networking, and Floating Point Arithmetic II (Chair: Byeong Kil Lee, University of Colorado)
    78 Investigating the Feasibility of FPGA-based Network Switches (Slides)
    Jiuxi Meng1, Nadeen Gebara1, Ho-Cheung Ng1, Paolo Costa2, Wayne Luk1
    Imperial College London1, Microsoft2
    12 A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter (Slides)
    Brett Mathis, James E. Stine
    Oklahoma State University
    73 (Short) SMPTE ST 2110 Compliant Scalable Architecture on FPGA for end to end Uncompressed Professional Video Transport over IP Networks (Slides)
    Nisal Ranasinghe1, Ravindu Bangamuarachchi1, Jayath Seneviratne1, Achini Jayawardane1, R.M.A.U. Senarath2, Ajith Pasqual1
    University of Moratuwa1, Paraqum Technologies2
    20:00-21:30 Social Event -- Top of the Rock, 30 Rockfeller Plaza, Enter on West 50th Street, New York City [direction] [more info]
    Wednesday July 17th (Tata Innovation Center, Room 023 & 131)
    09:00-09:40 Keynote IV (Chair: Zhiru Zhang, Cornell University)
    Towards High-Level Approaches to Hardware Cyber Security
    Ramesh Karri, NYU
    09:40-10:20 Invited Session: Hardware Acceleration II (Chair: Yun Eric Liang, Peking University)
    Graph-Morphing: Exploiting Hidden Parallelism of Non-Stencil Computation in High-Level Synthesis (Slides)
    Mingjie Lin, University of Central Florida
    Understanding Performance Gains of Accelerator-rich Architectures (Slides)
    Zhenman Fang1, Farnoosh Javadi2, Jason Cong2, Glenn Reinman2
    Simon Fraser University1, UCLA2
    10:20-10:40 Coffee Break
    10:40-11:20 Paper Session - Design Methodologies I (Chair: Zhenman Fang, Simon Fraser University)
    18 Base64 Encoding on Heterogeneous Computing Platforms (Slides)
    Zheming Jin, Hal Finkel
    Argonne National Laboratory
    25 Statistical Performance Prediction for Multicore Applications Based on Scalability Characteristics (Slides)
    Oliver Jakob Arndt, Matthias Lüders, Holger Blume
    Leibniz University Hannover
    11:20-12:20 Paper Session - Design Methodologies II (Chair: Zhenman Fang, Simon Fraser University)
    48 Molecular Dynamics Range-Limited Force Evaluation Optimized for FPGAs (Slides)
    Chen Yang1, Tong Geng1, Tianqi Wang1,2, Jiayi Sheng4, Charles Lin3, Vipin Sachdeva3, Woody Sherman3, Martin Herbordt1
    Boston University1, University of Science and Technology of China2, Silicon Therapeutics3, Falcon Computing4
    39 Refine and Recycle: A Method to Increase Decompression Parallelism (Slides)
    Jian Fang1, Jianyu Chen1, Jinho Lee2, Zaid Al-Ars1, H.Peter Hofstee1,2
    Delft University of Technology1, IBM Austin2
    62 Efficient Architectures and Implementation of Arithmetic Functions Approximation Based Stochastic Computing (Slides)
    Tieu-Khanh Luong1, Van-Tinh Nguyen2, Anh-Thai Nguyen3, Emanuel Popovici1
    University College Cork1, Nara Institute of Science and Technology2, Le Quy Don Technical University3
    57 (Short) Bank-Selective Strategy for Gate-based Ternary Content Addressable Memory on FPGAs (Slides)
    Muhammad Irfan1, Zahid Ullah2, Ray C. C. Cheung2
    City University of Hong Kong1, CECOS University of IT & Emerging Sciences2
    12:20-12:30 Closing Remarks and Best Paper Award Announcement (Slides)
    12:40-13:30 Lunch



Presentation guidelines

  • Long Papers You will be allocated 18 (15 mins presentation + 3 mins Q & A) minutes slot to present your paper.
  • Short Papers You will be allocated 5 minutes slot to present your paper with NO questions. You should focus on the key motivation and result and encourage the listeners to come your poster to discuss details with you.
  • Poster Papers You will be allocated 90 secs (1 technical slide limit) in the lightning poster session to present your poster paper. You should focus on the key motivation and encourage the listeners to come your poster to discuss details with you. The Monday lightning poster session (July 15) includes posters: 16, 24, 51, 99, 101, 102, 103, 106, 108. The Tuesday lightning poster session (July 16) includes posters: 21, 33, 53, 67, 93, 100, 110.
  • Short and Poster Papers In addition to giving a short presentation at the conference, you are also expected to present a poster of your paper at the Poster Session during lunch. The poster dimensions should be standard A1. You can find your poster session on the ASAP web page






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