Tentative Program

Presentation Guidelines

    Monday July 15th
    8:30-9:00 Registration
    9:00-9:15 Welcome Remarks
    9:15-10:00 Keynote (Chair: Zhiru Zhang)
    DNA Data Storage and Near-Molecule Processing for the Yottabyte Era

    Luis Ceze, University of Washington
    10:10-10:50 Paper Session – Applications: Machine Learning I (Chair: Roger Moussalli, Two Sigma)
    26 (Full) F-E3D: FPGA-based Acceleration of An Efficient 3D Convolutional Neural Network for Human Action Recognition
    Hongxiang Fan, Cheng Luo (Fudan university), Chenglong Zeng (Corerain Technologies), Martin Ferianc, Zhiqiang Que, Shuanglong Liu, Xinyu Niu, Wayne Luk (Imperial College London)
    80 (Full) LP-BNN: Ultra-low-Latency BNN Inference with Layer Parallelism
    Tong Geng, Tianqi Wang, Chunshu Wu, Chen Yang (Boston University), Shuaiwen Leon Song, Ang Li (Pacific Northwest National Laboratory), Martin Herbordt (Boston University)
    10:50-11:10 Coffee Break
    11:10-11:50 Paper Session – Applications: Machine Learning II (Chair: Roger Moussalli, Two Sigma)
    37 (Full) Efficient Weight Reuse for Large LSTMs
    Zhiqiang Que, Thomas Nugent (Imperial College London), Shuanglong Liu, Li Tian (Shanghai Advanced Research Institute, Chinese Academy of Sciences) , Xinyu Niu (Corerain Technologies Ltd.), Yongxin Zhu (Shanghai Advanced Research Institute, Chinese Academy of Sciences) ,Wayne Luk (Imperial College London)
    60 (Full) Photonic Processor for Fully Discretized Neural Networks
    Jeff Anderson, Shuai Sun, Yousra Alkabani, Volker Sorger, Tarek El-Ghazawi (The George Washington University)
    11:50-12:10 Lighting Session for Posters (Chair: Cunxi Yu, Cornell/UoUtah)
    16, 24, 51, 99, 101
    102, 103, 106, 108
    Poster papers (16, 24, 51, 99, 101, 102, 103, 106, 108)
    16 (Poster) Transparent Heterogeneous Cloud Acceleration
    Jessica Vandebon, Jose ́ G. F. Coutinho, Wayne Luk, Thomas Chau (Imperial College London)
    24 (Poster) CRbS:A Code Reordering based Speeding-up Method of Irregular Loops On CMP
    Li Yuancheng, Shi Jiaqi (Xi'an University of Science and Technology)
    51 (Poster) Impact of Structural Faults on Neural Network Performance
    Krishna Teja Chitty-Venkata and Arun Somani (Iowa State University)
    99 (Poster) Energy-Efficient Near-Sensor Convolution using Pulsed Unary Processing
    M. Hassan Najafi (University of Louisiana at Lafayette), S. Rasoul Faraji, Kia Bazargan, and David Lilja (University of Minnesota, Minneapolis)
    101 (Poster) An Efficient Application Specific Instruction Set Processor (ASIP) for Tensor Computation
    Wei-pei Huang, Ray C.C. Cheung, Hong Yan (City University of Hong Kong)
    102 (Poster) MITRACA: Manycore Interlinked Torus Reconfigurable Accelerator Architecture
    Riadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku (University of Tsukuba)
    106 (Poster) Using Residue Number Systems to Accelerate Deterministic Bit-stream Multiplication
    Kamyar Givaki(University of Tehran), Reza Hojabr(University of Tehran), M. Hassan Najafi(University of Louisiana at Lafayette), Ahmad Khonsari(University of Tehran, Tehran), M. H. Gholamrezayi(Shahid Beheshti University), Saeid Gorgin(Iranian Research Organization for Science and Technology), Dara Rahmati(Shahid Beheshti University)
    108 (Poster) Precision Adaptation for Fast and Accurate Polynomial Evaluation Generation
    Nicolas Brunie(Kalray S.A.), Christoph Lauter(University of Alaska Anchorage), Guillaume Revy(University of Perpignan Via Domitia, University of Montpellier)
    12:10-13:30 Lunch & Poster Session I
    Short papers (11, 49, 74, 96) and Posters (16, 24, 51, 99, 101, 102, 103, 106, 108)
    9:15-10:00 Keynote (Chair: Wayne Luk)
    From AI1.0, AI2.0, to XAI3.0

    Sun-Yuan Kung, Princeton University
    14:25-15:30 Paper Session - Architecture and Synthesis (Chair: Sang-Woo Jun, UC Irvine)
    9 (Full) Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays
    Bradley McDanel, HT Kung, Sai Qian Zhang, Xin Dong (Harvard University) , Chih Chiang Chen (MediaTek)
    43 (Full) Sparstition: A Partitioning Scheme for Large-Scale Sparse Matrix Vector Multiplication on FPGA
    Bjorn Sigurbergsson (TU Delft / Big Data Accelerate), Tom Hogervorst, Tong Dong Qiu (Big Data Accelerate) , Razvan Nane (TU Delft / Big Data Accelerate)
    31 (Full) End-to-end Dynamic Stream Processing on Maxeler HLS Platforms
    Charalampos Kritikakis, Dirk Koch (The University of Manchester)
    11 (Short) Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration
    Pareesa Ameneh Golnari (Google Corp), Sharad Malik (Princeton University)
    74 (Short) HelmGemm: Managing GPUs and FPGAs for transprecision GEMM workloads in containerized environments
    Dionysios Diamantopoulos (IBM Research - Zurich)
    15:30-15:50 Coffee Break
    15:50-17:00 Paper Session – Applications: Machine Learning, Robotics, and Simulation I (Chair: Bo Yuan, Rutgers)
    30 (Full) Error Analysis of the Square Root Operation for the Purpose of Precision Tuning: a Case Study on K-means
    Oumaima Matoussi, Yves Durand ,Olivier Sentieys, Anca Molnos (CEA, LETI, Univ. Grenoble Alpes)
    50 (Full) FPGA Architectures for Real-time Dense SLAM
    Quentin Gautier (UC San Diego) , Alric Althoff (UC San Diego) , Ryan Kastner (UC San Diego)
    28 (Full) Customizable Control Policy Learning for Robotics
    Ce Guo, Wayne Luk, Stanley Loh Qing Shui (Imperial College London), Alexander Warren and Joshua Levine (Intel)
    49 (Short) Resilient Neural Network Training for Accelerators with Computing Errors
    Dawen Xu (Institute of Computing Technology, Chinese Academy of Sciences) , Kouzi Xing (Hefei University of Technology), Cheng Liu, Ying Wang (Institute of Computing Technology, Chinese Academy of Sciences) , Yulin Dai (Hefei University of Technology), Long Cheng (University College Dublin), Huawei Li, Lei Zhang (Institute of Computing Technology, Chinese Academy of Sciences)
    76 (Short) VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing
    Dilshan Kumarathunga, Omega Gamage, Asitha Samarasinghe, Nipuna Saranga, Ranga Rodrigo, Ajith Pasqual (University of Moratuwa)
    17:30-21:00 Reception
    Tuesday July 16th
    09:00-09:45 Keynote (Chair: Yun (Eric) Liang, Peking University)
    Heterogeneous Systems Research - in the Mood for AI in the age of Cloud and IoT

    Jinjun Xiong, IBM
    10:00–10:40 Invited Paper Session: Hardware Acceleration (Chair: Yun (Eric) Liang, Peking University)
    Compiler Toolchain for Deep Learning Accelerators
    Salem Derisavi (Futurewei)
    PAI-FCNN: FPGA based inference system for complex CNN models
    Lixue Xia, Lansong Diao, Zhao Jiang, Hao Liang, Kai Chen, Li Ding, Shunli Dou, Zibin Su, Meng Sun, Jiansong Zhang, Wei Lin (Alibaba Group)
    10:40-11:00 Coffee Break
    11:10-11:45 Paper Session - Applications: Image Processing, Networking, and Floating Point Arithmetic I (Chair: Guojie Luo, Peking University)
    66 (Full) Event-Based Re-configurable Hierarchical Processors for Smart Image Sensors
    Pankaj Bhowmik, Md Jubaer Hossain Pantho, Christophe Bobda (University of Florida)
    69 (Full) OpenVX Graph Optimization for Visual Processor Units
    Madushan Abeysinghe (University of South Carolina), Jesse Villarreal,Lucas Weaver (Texas Instruments Corporation), Jason D. Bakos (University of South Carolina)
    44 (Short) Application Specific Architecture for Hardware Accelerating HOG-SVM to achieve High Throughput on HD Frames
    Piyumal Ranawaka (University of Moratuwa, Sri Lanka), Mongkol Ekpanyapong (Micro-electronics and Embedded Systems, Asian Institute of Technology, Thailand), Adriano Tavares (Department of Industrial Electronics, University of Minho, Portugal), Jorge Cabral (Department of ICT, Asian Institute of Technology, Thailand) ,Krit Athikulwongse (National Electronics and Computer Technology Center, National Science and Technology Development Agency, Thailand), Vitor Silva (Department of Industrial Electronics, University of Minho, Portugal)
    11:45-12:10 Lighting Session for Posters (Chair: Cunxi Yu, Cornell/UoUtah)
    21, 33, 53, 67, 93, 100, 110 Poster papers (21, 33, 53, 67, 93, 100, 110)
    21 (Poster) A Quantitative Approach for Refactoring NFV-based Mobile Core Networks
    Wei-Kuo Chiang, He-Xin Chen (National Chung Cheng University)
    33 (Poster) Fooling AI with AI: An Accelerator for Adversarial Attacks on Deep Learning Visual Classification
    Haoqiang Guo, Lu Peng, Jian Zhang, Fang Qi (Louisiana State University), Lide Duan (Alibaba Group)
    53 (Poster) A Virtual Image Accelerator for Graph Cuts Inference on FPGA
    Tianqi Gao (University of Illinois at Urbana Champaign), Rob A. Rutenbar (University of Pittsburgh)
    67 (Poster) Implications for Hardware Acceleration of Malware Detection
    Jordan Pattee, Byeong Kil Lee (University of Colorado, Colorado Springs)
    93 (Poster) GPUs Pipeline Latency Analysis
    Yehia Arafa, Abdel-Hameed A. Badawy (New Mexico State University), Gopinath Chennupati, Nandakishore Santhi, Stephan Eidenbenz (Los Alamos National Laboratory)
    100 (Poster) Context-Aware Number Generator for Deterministic Bit-stream Computing
    Sina Asadi and M. Hassan Najafi (University of Louisiana at Lafayette)
    110 (Poster) Smart Rabbit: A Wearable Device As Intelligent Pacer for Marathon Runners
    Wenpei Zheng, Sheng-Yang Chiu, Jui-Chien Hsieh, Chaochang Chiu (Yuan Ze University)
    12:10-13:30 Lunch & Poster Session II
    Short papers (17, 44, 57, 68, 73, 95) and Posters (21, 33, 53, 67, 93, 100, 110)
    13:20-14:20 Invited Paper Session: In Memory Computing (Chair: Zhiru Zhang, Cornell University)
    Real Processing-in-Memory with Memristive Memory Processing Unit
    Shahar Kvatinsky (Technion – Israel Institute of Technology)
    PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations
    Oscar Castañeda, Maria Bobbett, Alexandra Gallyas-Sanhueza, and Christoph Studer (Cornell University)
    Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design
    Feng Wang, Guojie Luo, Guangyu Sun, Jiaxi Zhang, Peng Huang, Jinfeng Kang (Peking University)
    14:30-15:20 Paper session – Applications: Machine Learning, Robotics, and Simulation II (Chair: Jiemin Yin, AMD)
    71 (Full) An Overlay Architecture for High-Throughput Pattern Matching
    Rasha Karakchi, Charles A. Daniels, Jason D. Bakos (University of South Carolina)
    59 (Full) Towards Real Time Radiotherapy Simulation
    Nils Voss (Imperial College London) ,Peter Ziegenhein (Joint Department of Physics at The Institute of Cancer Research and The Royal Marsden NHS Foundation Trust) , Lukas Vermond, Joost Hoozemans, Oskar Mencer, Uwe Oelfke (Maxeler Technologies), Wayne Luk (Imperial College London), Georgi Gaydadjiev (Maxeler Technologies)
    68 (Short) Accelerating AP3M-Based Computational Astrophysics Simulations with Reconfigurable Clusters
    Tianqi Wang (University of Science and Technology of China) ,Tong Geng (Boston University) ,Xi Jin (University of Science and Technology of China), Martin Herbordt (Boston University)
    17 (Short) A Programmable Architecture for Robot Motion Planning Acceleration
    Sean Murray, Will Floyd-Jones (Duke University) ,George Konidaris (Brown University), Dan Sorin (Duke University)
    15:20-15:40 Coffee Break
    15:40-16:40 Paper Session - Emerging Technologies (Chair: Jason Bakos , University of South Carolina)
    109 (Full) Leveraging Energy Cycle Regularity to Predict Adaptive Mode for Non-volatile Processors
    Zejun Shi (Tsinghua University), Dongqin Zhou, Keni Qiu (Capital Normal University), Jiwu Shu (Tsinghua University)
    58 (Full) An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators
    Saunak Saha, Henry Duwe, Joseph Zambreno (Iowa State University)
    10 (Full) Improving Emulation of Quantum Algorithms using Space-Efficient Hardware Architectures
    Naveed Mahmud, Esam El-Araby (University of Kansas)
    95 (Short) Combining Clock and Voltage Noise Countermeasures against Power Side-Channel Analysis
    Jacqueline Lagasse, Christopher Bartoli, Wayne Burleson (University of Massachusetts Amherst)
    16:40-17:30 Paper Session - Applications: Image Processing, Networking, and Floating Point Arithmetic II (Chair: Byeong Kil Lee, University of Colorado)
    78 (Full) Investigating the Feasibility of FPGA-based Network Switches
    Jiuxi Meng, Nadeen Gebara, Ho-Cheung Ng (Imperial College London), Paolo Costa (Microsoft), Wayne Luk (Imperial College London)
    12 (Full) A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter
    Brett Mathis, James E. Stine (Oklahoma State University)
    73 (Short) SMPTE ST 2110 Compliant Scalable Architecture on FPGA for end to end Uncompressed Professional Video Transport over IP Networks
    Nisal Ranasinghe, Ravindu Bangamuarachchi, Jayath Seneviratne, Achini Jayawardane, R.M.A.U. Senarath, Ajith Pasqual (University of Moratuwa, Sri Lanka)
    17:30-21:00 Social Event
    Wednesday July 17th
    09:00-10:00 Invited Paper Session: Hardware Acceleration II (Chair: Yun Eric Liang, Peking University)
    Graph-Morphing: Exploiting Hidden Parallelism of Non-Stencil Computation in High-Level Synthesis
    Mingjie Lin (UCF)
    Agile FPGA Design
    Justin Thiel (Two Sigma)
    Understanding Performance Gains of Accelerator-rich Architectures
    Zhenman Fang (Simon Fraser University), Farnoosh Javadi, Jason Cong, Glenn Reinman (UCLA)
    10:10-10:50 Paper Session - Design Methodologies I (Chair: Zhenman Fang, SFU)
    18 (Full) Base64 Encoding on Heterogeneous Computing Platforms
    Zheming Jin, Hal Finkel (ANL)
    25 (Full) Statistical Performance Prediction for Multicore Applications Based on Scalability Characteristics
    Oliver Jakob Arndt, Matthias Lüders, Holger Blume (Leibniz University Hannover, Inst. of. Microelectronic Systems)
    10:50-11:10 Coffee Break
    11:10-12:10 Paper Session - Design Methodologies II (Chair: Zhenman Fang, SFU)
    48 (Full) Molecular Dynamics Range-Limited Force Evaluation Optimized for FPGAs
    Chen Yang,Tong Geng,Tianqi Wang (Boston University) ,Jiayi Sheng (Falcon Computing Solutions, Inc.) ,Charles Lin, Vipin Sachdeva, Woody Sherman (Silicon Therapeutics), Martin Herbordt (Boston University)
    39 (Full) Refine and Recycle: A Method to Increase Decompression Parallelism
    Jian Fang, Jianyu Chen (Delft University of Technology) ,Jinho Lee (IBM Austin) ,Zaid Al-Ars (Delft University of Technology), H.Peter Hofstee (IBM Austin & Delft University of Technology)
    62 (Full) Efficient Architectures and Implementation of Arithmetic Functions Approximation Based Stochastic Computing
    Tieu-Khanh Luong (Department of Electrical & Electronic Engineering, and MCCI, University College Cork, Ireland) ,Van-Tinh Nguyen (School of Information Science, Nara Institute of Science and Technology, Japan), Anh-Thai Nguyen (Le Quy Don Technical University, 236 Hoang Quoc Viet Str., Hanoi, Vietnam), Emanuel Popovici (Department of Electrical & Electronic Engineering, and MCCI, University College Cork, Ireland)
    57 (Short) Bank-Selective Strategy for Gate-based Ternary Content Addressable Memory on FPGAs
    Muhammad Irfan (City University of Hong Kong, Hong Kong), Zahid Ullah (CECOS University of IT & Emerging Sciences, Pakistan), Ray C. C. Cheung (City University of Hong Kong, Hong Kong)
    12:10-12:30 Closing Remarks and Best Paper Award Announcement
    12:30-13:30 Lunch

 

 

Presentation guidelines

  • Long Papers You will be allocated 18 (15 mins presentation + 3 mins Q & A) minutes slot to present your paper.
  • Short Papers You will be allocated 5 minutes slot to present your paper with NO questions. You should focus on the key motivation and result and encourage the listeners to come your poster to discuss details with you.
  • Poster Papers You will be allocated 90 secs (1 technical slide limit) in the lighting poster session to present your poster paper. You should focus on the key motivation and encourage the listeners to come your poster to discuss details with you. The Monday lighting poster session (July 15) includes posters: 16, 24, 51, 99, 101, 102, 103, 106, 108. The Tuesday lighting poster session (July 16) includes posters: 21, 33, 53, 67, 93, 100, 110.
  • Short and Poster Papers In addition to giving a short presentation at the conference, you are also expected to present a poster of your paper at the Poster Session during lunch. The poster dimensions should be standard A1. You can find your poster session on the ASAP web page https://asap2019.csl.cornell.edu/program.html.

 

 

 

 

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